1 ps2039b 02/24/99 logic block diagram 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct16646t pi74fct162646t PI74FCT162H646T product description pericom semiconductor?s pi74fct series of logic circuits are pro duced in the company?s advanced 0.6 micron cmos technology, achieving industry leading speed grades. the pi74fct16646t, pi74fct162646t, and pi74fct162h646 are 16-bit registered transceivers organized as two independent 8-bit bus transceivers designed with 3-state d-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. each 8-bit transceiver utilizes the enable control (xoe) and direction pins (xdir) to control the transceiver functions. the select (xsab and xsba) control pins are used to select either real-time or stored data transfer. the circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between real-time and stored data. a low input level selects real-time data and a high selects stored data. the pi74fct16646t output buffers are designed with a power-off disable allowing ?live insertion? of boards when used as backplane drivers. the pi74fct162646t has 24ma balanced output drivers. it is designed with current limiting resistors at its outputs to control the output edge rate resulting in lower ground bounce and undershoot. this eliminates the need for external terminating resistors for most interface applications. the PI74FCT162H646T has ?bus hold? which retains the input?s last state whenever the input goes to high-impedance preventing ?floating? inputs and eliminating the need for pull-up/down resistors. product features common features: ? pi74fct16646t, pi74fct162646t, and pi74fct162h646 are high-speed, low power devices with high current drive ?v cc = 5v 10% ? hysteresis on all inputs ? packages available: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 173 mil wide plastic tvsop (jedec tssop k) ? 56-pin 300 mil wide plastic ssop (v) pi74fct16646t features: ? high output drive: i oh = ?32ma; i ol = 64ma ? power off disable outputs permit ?live insertion? ? typical v olp (output ground bounce) < 1.0v at v cc = 5v, t a = 25c pi74fct162646t features: ? balanced output drivers: 24ma ? reduced system switching noise ? typical v olp (output ground bounce) < 0.6v at v cc = 5v, t a = 25c PI74FCT162H646T features: ? bus hold retains last active bus state during three-state ? eliminates the need for external pull-up resistors 1 fast cmos 16-bit registered transceivers d 1 clkab c 1 clkba 1 sba 1 dir 1 oe 1 sab d c a reg b reg 1 b0 1 a0 to 7 other channels d 2 clkab c 2 clkba 2 sba 2 dir 2 oe 2 sab d c a reg b reg 2 b0 2 a0 to 7 other channels
pi74fct16646t/162646t/162h646t 16-bit registered transceivers 2 ps2039b 02/24/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 32 31 30 29 1 dir 1 clkab 1 sab gnd 1 a 0 1 a 1 vcc 1 a 2 1 a 3 1 a 4 gnd 1 a 5 1 a 6 1 a 7 2 a 0 2 a 1 2 a 2 gnd 2 a 3 2 a 4 2 a 5 v cc 2 a 6 2 a 7 gnd 2 sab 2 clkab 2 dir 1 oe 1 clkba 1 sba gnd 1 b 0 1 b 1 vcc 1 b 2 1 b 3 1 b 4 gnd 1 b 5 1 b 6 1 b 7 2 b 0 2 b 1 2 b 2 gnd 2 b 3 2 b 4 2 b 5 v cc 2 b 6 2 b 7 gnd 2 sba 2 clkba 2 oe product pin configuration notes : 1.the data output functions may be enabled or disabled by various signals at the xoe or xdir inputs. data input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs. 2. select control = l: clocks can occur simultaneously. select control = h: clocks must be staggered to load both registers. h = high voltage level; l = low voltage level; x = dont care; - = low-to-high transition pin name description xax (1) data register a inputs data register b outputs xbx (1) data register b inputs data register a outputs xclkab, xclkba clock pulse inputs sab, sba output data source select inputs xdir, xoe output enable inputs gnd ground v cc power note : 1.for the PI74FCT162H646T, these pins have bus hold. all other pins are standard, outputs, or i/os. product pin description inputs data i/o (2) function/operation xoe x dir x clkab x clkba x sab x sba x a xx b x isolation h x h or l h or l x x input input store a and b data h x -- xx real time b data to a bus l l x x x l output input stored b data to a bus l l x h or l x h real time a data to b bus l h x x l x input output stored a data to b bus l h h or l x h x truth table 56-pin v56 a56 k56
pi74fct16646t/162646t/162h646t 16-bit registered transceivers 3 ps2039b 02/24/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 real-time transfer bus b to a real-time transfer bus a to b storage from a and/or b transfer stores data to a and/or b xdir xoe xclkab xclkba xsab xsba hl x x x ll x x x xh x x xdir xoe xclkab xclkba xsab xsba l l x h or l x h h l h or l x h x bus a bus b bus a bus b xdir xoe xclkab xclkba xsab xsba ll x x x l xdir xoe xclkab xclkba xsab xsba hl x x l x bus a bus b bus a bus b
pi74fct16646t/162646t/162h646t 16-bit registered transceivers 4 ps2039b 02/24/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 dc electrical characteristics (over the operating range, t a = ?40c to +85c, v cc = 5.0v 10%) parameters description test conditions (1) min. typ. (2) max. units v ih input high voltage guaranteed logic high level 2.0 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current standard input, v cc = max. v in = v cc 1a i ih input high current standard i/o, v cc = max. v in = v cc 1a i ih input high current bus hold input (4) , v cc = max. v in = v cc 100 a i ih input high current bus hold i/o (4) , v cc = max. v in = v cc 100 a i il input low current standard input, v cc = min. v in = gnd ?1 a i il input low current standard i/o, v cc = min. v in = gnd ?1 a i il input low current bus hold input (4) , v cc = min. v in = gnd 100 a i il input low current bus hold i/o (4) , v cc = min. v in = gnd 100 a i bhh bus hold bus hold input (4) , v cc = min. v in = 2.0v ?50 a i bhl sustain current v in = 0.8v +50 i ozh (5) high-impedance v cc = max. v out = 2.7v 1 a i ozl (5) output current v cc = max. v out = 0.5v ?1 a (3-s tate o utputs ) v ik clamp diode voltage v cc = min., i in = ?18ma ?0.7 ?1.2 v i os short circuit current v cc = max. (3) , v out = gnd ?80 ?140 ?200 ma i o output drive current v cc = max. (3) , v out = 2.5v ?50 ?180 ma v h input hysteresis 100 mv storage temperature ................................................................. C65c to +150c ambient temperature with power applied ................................ C40c to +85c supply voltage to ground potential (inputs & vcc only) .......... C0.5v to +7.0v supply voltage to ground potential (outputs & d/o only) ....... C0.5v to +7.0v dc input voltage ......................................................................... C0.5v to +7.0v dc output current .................................................................................... 120ma power dissipation ......................................................................................... 1.0w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. pins with bus hold are identified in the pin description. 5. this specification does not apply to bi-directional functionalities with bus hold. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.)
pi74fct16646t/162646t/162h646t 16-bit registered transceivers 5 ps2039b 02/24/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct16646t output drive characteristics (over the operating range) parameters description test conditions (1) min. typ. (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = C3.0ma 2.5 3.5 v i oh = C15.0ma 2.4 3.5 i oh = C32.0ma 2.0 3.0 v ol output low voltage v cc = min., v in = v ih or v il i ol = 64ma 0.2 0.55 v i off power down disable v cc = 0v, v in or v out 4.5v 100 a pi74fct162646t/162h646t output drive characteristics (over the operating range) parameters description test conditions (1) min. typ. (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = ?24.0ma 2.4 3.3 v v ol output low voltage v cc = min., v in = v ih or v il i ol = 24ma 0.3 0.55 v i odl output low current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) 60 115 150 ma i odh output high current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) ?60 ?115 ?150 ma notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is determined by device characterization but is not production tested. capacitance (t a = 25c, f = 1 mhz) parameters (4) description test conditions typ. max. units c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf
pi74fct16646t/162646t/162h646t 16-bit registered transceivers 6 ps2039b 02/24/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 power supply characteristics parameters description test conditions (1) min. typ. (2) max. units i cc quiescent power v cc = max. v in = gnd or v cc 0.12 500 a supply current d i cc supply current per v cc = max. v in = 3.4v (3) 0.5 1.5 ma input @ ttl high i ccd supply current per v cc = max., outputs open v in = v cc 75 120 a/ input per mhz (4) xdir = xoe = gnd v in = gnd mhz one bit toggling 50% duty cycle i c total power supply v cc = max., v in = v cc 0.8 1.7 (5) ma current (6) outputs open v in = gnd f cp = 10 mh z ( x clkba) 50% duty cycle xdir = xoe = gnd one bit toggling v in = 3.4v 1.3 3.2 (5) f i = 5 mh z v in = gnd 50% duty cycle v cc = max., v in = v cc 3.8 6.5 (5) outputs open v in = gnd f cp = 10 mh z ( x clkba) 50% duty cycle xdir = xoe = gnd 16 bits toggling v in = 3.4 8.3 20.0 (5) f i = 2.5 mh z v in = gnd 50% duty cycle notes: 1. for max. or min. conditions use appropriate value specified under electrical characteristics for the applicable device. 2. typical values are at vcc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at vcc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the icc formula. these limits are guaranteed but not tested. 6. i c =i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz.
pi74fct16646t/162646t/162h646t 16-bit registered transceivers 7 ps2039b 02/24/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct16646t switching characteristics over operating range 16646t 16646at 16646ct 16646dt 16646et com. com. com. com. com. parameters description conditions (1) min. max. min. max. min. max. min. max. min. max. units t plh propagation delay c l = 50 pf 2.0 9.0 2.0 6.3 1.5 5.4 1.5 4.4 1.5 3.8 ns t phl bus to bus r l = 500 w t pzh output enable time 2.0 14.0 2.0 9.8 1.5 7.8 1.5 5.0 1.5 4.8 ns t pzl xdir or xoe to bus t phz output disable time (3) 2.0 9.0 2.0 6.3 1.5 6.3 1.5 4.3 1.5 4.0 ns t plz xdir or xoe to bus t plh propagation delay 2.0 9.0 2.0 6.3 1.5 5.7 1.5 4.4 1.5 3.8 ns t phl clock to bus t plh propagation delay 2.0 11.0 2.0 7.7 1.5 6.2 1.5 5.0 1.5 4.2 ns t phl xsba or xsab to bus t su setup time high or 4.0 2.0 2.0 2.0 2.0 ns low, b us to clock t h hold time high or 2.0 1.5 1.5 1.0 0.0 ns low, bus to clock t w clock pulse width 6.0 5.0 5.0 3.0 3.0 ns high or low (3) t sk (o) output skew (4) 0.5 0.5 0.5 0.5 0.5 ns pi74fct162646t switching characteristics over operating range 162646t 162646at 162646ct 162646dt 162646et com. com. com. com. com. parameters description conditions (1) min. max. min. max. min. max. min. max. min. max. units t plh propagation delay c l = 50 pf 2.0 9.0 2.0 6.3 1.5 5.4 1.5 4.4 1.5 3.8 ns t phl bus to bus r l = 500 w t pzh output enable time 2.0 14.0 2.0 9.8 1.5 7.8 1.5 5.0 1.5 4.8 ns t pzl xdir or xoe to bus t phz output disable time (3) 2.0 9.0 2.0 6.3 1.5 6.3 1.5 4.3 1.5 4.0 ns t plz xdir or xoe to bus t plh propagation delay 2.0 9.0 2.0 6.3 1.5 5.7 1.5 4.4 1.5 3.8 ns t phl clock to bus t plh propagation delay 2.0 11.0 2.0 7.7 1.5 6.2 1.5 5.0 1.5 4.2 ns t phl xsba or xsab to bus t su setup time high or 4.0 2.0 2.0 2.0 2.0 ns low, b us to clock t h hold time high or 2.0 1.5 1.5 1.0 0.0 ns low, bus to clock t w clock pulse width 6.0 5.0 5.0 3.0 3.0 ns high or low (3) t sk (o) output skew (4) 0.5 0.5 0.5 0.5 0.5 ns notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not production tested. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design.
pi74fct16646t/162646t/162h646t 16-bit registered transceivers 8 ps2039b 02/24/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI74FCT162H646T switching characteristics over operating range 162h646t 162h646at 162h646ct 162h646dt 162h646et com. com. com. com. com. parameters description conditions (1) min. max. min. max. min. max. min. max. min. max. units t plh propagation delay c l = 50 pf 2.0 9.0 2.0 6.3 1.5 5.4 1.5 4.4 1.5 3.8 ns t phl bus to bus r l = 500 w t pzh output enable time 2.0 14.0 2.0 9.8 1.5 7.8 1.5 5.0 1.5 4.8 ns t pzl xdir or xoe to bus t phz output disable time (3) 2.0 9.0 2.0 6.3 1.5 6.3 1.5 4.3 1.5 4.0 ns t plz xdir or xoe to bus t plh propagation delay 2.0 9.0 2.0 6.3 1.5 5.7 1.5 4.4 1.5 3.8 ns t phl clock to bus t plh propagation delay 2.0 11.0 2.0 7.7 1.5 6.2 1.5 5.0 1.5 4.2 ns t phl xsba or xsab to bus t su setup time high or 4.0 2.0 2.0 2.0 2.0 ns low, b us to clock t h hold time high or 2.0 1.5 1.5 1.0 0.0 ns low, bus to clock t w clock pulse width 6.0 5.0 5.0 3.0 3.0 ns high or low (3) t sk (o) output skew (4) 0.5 0.5 0.5 0.5 0.5 ns notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not production tested. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design. pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com
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